1. Field of the Invention
The invention relates to semiconductor technology and more particularly to a light sensing device.
2. Description of the Related Art
In a wafer level packaging process for semiconductor devices, a post passivation interconnection (PPI) structure is formed for redistribution of pads on semiconductor chips in order to effectively use the surface area of chips to reduce package size. The PPI structure typically comprises a wiring redistribution layer and a passivation layer. A terminal of the wiring redistribution layer is not covered by the passivation layer. The PPI structure usually suffers from poor adhesion between the wiring redistribution layer and the passivation layer thereof, and from poor adhesion between the terminal of the wiring redistribution layer and a connecting device connecting the terminal with an exterior device, thus negatively affecting the reliability of the packaged semiconductor devices.
Meanwhile, with requirements for denser circuit routing and smaller semiconductor chip sizes, it is necessary to increase the layers of metal line patterns and decrease the line pitch to effectively connect every individual element in semiconductor chips. A plurality of layers of insulating films or materials are typically called inter-layer dielectric (ILD) layers for isolating metal interconnections of different levels. Silicon oxide is usually utilized as the ILD layers, wherein a dielectric constant is between 4.0 and 4.5. However, with shorter metal line pitch, the capacitance value in a layer or between layers increases because the capacitance value is inversely proportional to line pitch, increasing the RC delay time. With the increased RC delay time negatively affecting the signal communication time in the circuit, it is necessary to decrease the dielectric constant of the ILD layers to improve circuit performance, such as clock responses.
Dielectric materials with dielectric constant of less than 3 are typically called low k dielectric materials. When low k dielectric materials are utilized as the dielectric layers between metal lines, the adhesive strength between the low k materials and metals are lower than that between silicon oxide and metals. As such, ILD layers of the low k dielectric materials often peel due to exterior mechanical stress during the semiconductor packaging process or operation of packaged semiconductor devices, thus negatively affecting device performance or causing device malfunction.